1. Field of the Invention
The present invention relates to an analog buffer and a method for driving the same, and more particularly, to an analog buffer and a method for driving the same capable of reducing power consumption and reliably supplying an output voltage in driving a signal line of a flat panel display device.
2. Description of the Related Art
In general, thin film type flat panel display devices with screens displaying image information have been actively developed in recent years because they are light weight and can be easily used anywhere. Particularly, research into liquid crystal display (LCD) devices is actively ongoing because of their high resolution and a fast reaction speed in order to implement a dynamic image.
By artificially controlling an alignment direction of liquid crystal molecules having a directional characteristic to affect polarization, the liquid crystal display device can transmit or block light by optical anisotropy according to the alignment direction of a liquid crystal. By using this property, the liquid crystal display device may be used as a flat panel display device. Active matrix LCDs with a plurality of pixels arranged in a matrix display image information that is selectively provided to each pixel through a switching element such as a thin film transistor (TFT) provided at each pixel. Active matrix LCDs are being used most generally because they provide excellent image quality.
A substrate used for the liquid crystal display device is made of a transparent material which transmits light, such as a glass material which is low cost and easily processed.
If the transistor is made of a polycrystalline silicon material having high electron mobility, it has a fast switching speed, and it can be designed to be small. However, because polycrystalline silicon is typically formed using a high temperature process, it cannot be formed on a glass substrate of the liquid crystal display device.
In this, the thin film transistor applied on the glass substrate of the liquid crystal display device is made of an amorphous silicon material.
A driving unit of the liquid crystal display device is formed of a plurality of integrated circuits (IC) having fast switching speeds and small-sized transistors integrated at a high density because many switching elements are required in order to process a digital signal.
Accordingly, the transistors used in the driving unit of the liquid crystal display device should be made of a polycrystalline silicon material formed by a high temperature process.
As mentioned above, the thin film transistor applied to the substrate of the liquid crystal display device is made of an amorphous silicon material by a low temperature process, and the transistor applied to the driving unit of the liquid crystal display device is made of a polycrystalline silicon material formed by a high temperature process.
Accordingly, the driving unit of the liquid crystal display device includes a plurality of integrated circuits which are individually fabricated on a separate single crystal silicon substrate and a tape carrier package (TCP) on which the integrated circuits are mounted, and the driving unit is connected to a substrate of a liquid crystal display device by a tape automated bonding (TAB) method. Alternatively, the driving unit includes a plurality of integrated circuits which are individually fabricated on a separate single crystal silicon substrate and is mounted on the substrate of the liquid crystal display device by a chip-on-glass (COG) method to be coupled to the substrate.
However, in case where the driving unit of the liquid crystal display device is coupled to the substrate by the TAB method or the chip-on-glass method, the miniaturization and the simplification of the liquid crystal display device is limited because the space occupied by the driving unit of the liquid crystal display device is required. As lines for transmitting driving signals are increased in number and length, various noise, electromagnetic interference (EMI) or the like are generated, thereby degrading the reliability and increasing the fabrication cost of the liquid crystal display device.
Therefore, research into forming the polycrystalline silicon by a low temperature process have been recently developed so that it has become possible to make a thin film transistor fabricated on a substrate of the liquid crystal display device by using a polycrystalline silicon material. Accordingly, a driving circuit-integrated liquid crystal display device in which the driving unit is formed on a substrate of the liquid crystal display device has been proposed.
FIG. 1 is an exemplary view showing a schematic structure of the driving circuit-integrated liquid crystal display device.
Referring to FIG. 1, the liquid crystal display device includes a liquid crystal display panel 10 in which gate lines located at regular intervals and arranged horizontally and data lines 30 located at regular intervals and arranged vertically cross, and pixels 40 are formed in a square area formed as the gate lines 20 and the data lines 30 cross; a gate driving unit 50 mounted on the liquid crystal display panel 10, for applying a scan signal to the gate lines 20; and a data driving unit 60 mounted on the liquid crystal display panel 10, for applying a data signal to the data lines 30.
A pixel electrode and a thin film transistor are provided at each pixel 40. The thin film transistor includes a gate electrode connected to the gate line 20; a source electrode connected to the data line 30; and a drain electrode connected to the pixel electrode.
A gate pad part and a data pad part are formed at one end of gate lines 20 and data lines 30.
The gate driving unit 50 sequentially applies a scan signal to the gate lines 20 through the gate pad part, and the data driving unit 60 applies a data signal to the data lines 30 through the data pad part, so that pixels 40 of the liquid crystal display panel 10 are individually driven, and thus a desired image is displayed on the liquid crystal display panel 10.
The gate driving unit 50 and the data driving unit 60 mounted at the liquid crystal display panel 10 are simultaneously fabricated in a process for fabricating a thin film transistor array substrate of the liquid crystal display panel 10.
As liquid crystal display devices are developed with high resolution and large size, the data lines and the gate lines increase in number and length, thereby increasing a load on the driving circuit. The same is true with respect to the number of data signals which are processed in order to drive the liquid crystal display device. Therefore, the driving unit of the liquid crystal display device has to be driven at a faster speed. However, due to the increased load on the data lines and the gate lines, a desired signal cannot be applied within a short period of time.
Accordingly, large-sized and high resolution liquid crystal display devices necessarily require an analog buffer which can apply a desired signal within a short period of time, corresponding to the load of the data lines and the gate lines.
In general, because transistors with a single crystal silicon material have fine electrical property differences, an operational amplifier is designed and so can be applied as the analog buffer. On the contrary, because transistors with a polycrystalline silicon material have great electrical property differences, an operational amplifier designed with the polycrystalline silicon transistors has a great offset voltage and consumes a large amount of power due to a static current. For this reason, it is difficult to apply the operation amplifier of the polycrystalline silicon material as the analog buffer.
Accordingly, the driving circuit-integrated liquid crystal display device requires an analog buffer that is insensitive to electrical property differences of the transistors made of polycrystalline silicon material, has a simple structure so as to reduce an area occupied thereby and consumes a small amount of power.
The conventional analog buffer as mentioned above will now be described in detail with reference to the accompanying drawings.
FIG. 2 is an exemplary view showing a conventional analog buffer. The analog buffer includes a comparing unit (COMP1) for calibrating a voltage change of an output signal (OUT_SIG) applied to a data line upon receiving an analog signal (ANALOG_SIG) through a first switch (SW1) and a first capacitor (C1); a second switch (SW2) connected between an input terminal and an output terminal of the comparing unit (COMP1); and a third switch (SW3) connected to the output terminal of the comparing unit (COMP1) and between the first switch (SW1) and the first capacitor (C1).
The first switch (SW1) and the second switch (SW2) are simultaneously turned on and off by a first control signal (CS1), and the third switch (SW3) is turned on and off by a second control signal.
FIG. 3 is a wave form view of an analog buffer illustrated in FIG. 2, and a drive of the conventional analog buffer will now be described in detail with reference thereto.
First, during an initializing period the first control signal (CS1) is applied with a high potential, the first switch (SW1) is turned on so that an analog signal (ANALOG_SIG) is charged at a first capacitor (C1), and the second (SW2) is also turned on so that an input terminal and an output terminal of the comparing unit (COMP1) are initialized. At this time, because the second control signal (CS2) is at a low potential, the third switch (SW3) is turned off.
Accordingly, a voltage (Vana−Vth) obtained by subtracting a threshold voltage (Vth) of the comparing unit (COMP1) from a voltage value (Vana) of the analog signal (ANALOG_SIG) is charged at the first capacitor (C1) during the initializing period.
The third switch (SW3) is turned on when the second control signal (CS2) is set to a high potential, so that a voltage (Vana) of the analog signal (ANALOG_SIG) is applied to a data line (D1) as an output signal (OUT_SIG) through the turned-on third switch (SW3). At this time, because the first control signal (CS1) is set to a low potential, the first switch (SW1) and the second switch (SW2) are turned off.
In order to calibrate an error due to electrical property differences of transistors in the comparing unit (COMP1), during the initializing period, the conventional analog buffer driven as above stores an offset voltage at the first capacitor (C1) and simultaneously initializes the input terminal and the output terminal of the comparing unit (COMP1).
A voltage value (Vana) of the analog signal (ANALOG_SIG) is applied to a data line (D1) as an output signal (OUT_SIG) through the turned-on third switch (SW3) during the signal-applied period.
When a voltage of an output signal (OUT_SIG) applied to the data line (D1) is changed, the comparing unit (COMP1) changes a voltage of the input terminal to pull up or pull down a voltage value (Vana) of the analog signal (ANALOG_SIG), together with the first capacitor (C1).
That is, when a voltage of an output signal (OUT_SIG) applied to the data line (D1) is raised, a voltage of the input terminal of the comparing unit (COMP1) is dropped, and the comparing unit (COMP1) pulls down a voltage value (Vana) of the analog signal (ANALOG_SIG), together with the first capacitor (C1). On the contrary, when a voltage of the output signal (OUT_SIG) applied to the data line (D1) is dropped, a voltage of the input terminal of the comparing unit (COMP1) is raised, and the comparing unit (COMP1) pulls up a voltage value (Vana) of the analog signal (ANALOG_SIG) together with the first capacitor (C1).
The voltage value (Vana) of the analog signal (ANALOG_SIG) pulled up or down as above is applied to the data line (D1) as an output signal (OUT_SIG) through the third switch (SW3). Thus, a voltage change of the output signal (OUT_SIG) is calibrated, and the calibrated voltage is applied to the data line (D1).
However, because the conventional analog buffer above is driven in a state that an offset voltage is applied to the input terminal of the comparing unit (COMP1), a leakage current flows from the comparing unit (COMP1). In the case of a high resolution, large-sized liquid crystal display device, in which a load of a data line (D1) connected to an output terminal of the comparing unit (COMP1) is large, the comparing unit (COMP1) has to be designed to be big, thereby increasing a leakage current and thus increasing power consumption.
In addition, by controlling the voltage at an input terminal of the comparing unit (COMP1) according to a voltage change of the output signal (OUT_SIG) applied to the data line (D1) and applying the voltage as an output signal (OUT_SIG), a voltage change of the output signal (OUT_SIG) is calibrated. Accordingly, an output signal, the voltage change of which has been calibrated, may overshoot a voltage value of the data signal, and thus a desired color image may not be displayed on a flat panel display device.